This invention relates to a method of manufacturing a MOS transistor by large-tilt-angle ion implantation.
In the conventional a method of manufacturing a MOS transistor in particular, an n-channel MOS transistor in order to obtain a highly reliable drain-sustaining voltage, after forming a gate electrode, a low concentration of ions are implanted using the gate electrode as a mask to form first source and drain regions, and a sidewall is formed on each side of the gate electrode of an insulating film, and a high concentration of ions are implanted using the gate electrode and sidewall as a mask to form second source and drain regions, thereby forming a MOS transistor having an LDD (lightly doped drain) structure (e.g. IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982).
As an example of such process, a manufacturing method of an n-channel LDD structure MOS transistor described below while referring to FIG. 1. First, after isolating elements on a P-type semiconductor substrate 1, a gate insulator film 2 is formed, and a polysilicon film is deposited and etched to form a gate electrode 3 [FIG. 1 (a)]. Next, in order to form LDD regions (n- layer) 4s, 4d, ions of a low concentration A (using phosphorus in this case) are implanted, using the gate electrode 3 as a mask [FIG. 1 (b)]. Afterwards, a CVD-SiO.sub.2 film 6 is formed [FIG. 1 (c)], and by anisotropic etching of the CVD-SiO.sub.2 film 6, the CVD-SiO.sub.2 film 6 formed on the flat surface is removed, and a sidewall 7 made of the CVD-SiO.sub.2 film 6 is obtained on the periphery of the gate electrode 3 [FIG. 1 (d)]. Next, in order to form the desired source and drain regions (n+ layer) 5s, 5d, ions of a high concentration B (using arsenic) are implanted using both of the gate electrode 3 and sidewalls 7 as a mask [FIG. 1 (e)]. At this time, the sidewall 7 CVD-SiO.sub.2 film 6 impedes the ion implantation into the surface of the semiconductor substrate 1, and the LDD regions (n- layer) 4s, 4d remain between the source and drain regions (n+ layer) 5s, 5d. Finally, by heat treatment, an n-channel LDD structure MOS transistor is formed as shown in FIG. 1 (e).
Thus, in the conventional LDD structure MOS transistor, the LDD regions (n- layer) 4s, 4d operate lessen the drain electric field, and a high reliability is obtained in the brain-sustaining Voltage, etc.
In the conventional LDD structure MOS transistors, however, as shown in FIG. 1 (e), since the majority of the LDD region (n- layer) 4s, 4d is generally located outside, not immediately beneath the gate electrode 3, the LDD region located outside the gate electrode 3 is pinched off, which tends to be a high resistance layer. Accordingly, as compared with the conventional single source/drain structure MOS transistor, the LDD structure MOS transistor has the following disadvantages.
(1) Since the high resistance layer intervenes in series, the driving current drops. Particularly in a high gate-drive voltage.
(2) As hot electrons are injected into the sidewall 7, the n- layers 4s, 4d immediately beneath the sidewall 7 are pinched off, and are extremely increase in resistance. Accordingly, as compared with the conventional single source/drain structure MOS transistor, deterioration of the driving current due to hot electrons takes place earlier, which is a serious reliability problem.
On the other hand, in a p-channel MOS transistor using an n+ poly-Si gate, a buried channel structure of the same conductive type as the source and drain regions is employed. In such a buried-channel transistor, however, as the channel length becomes shorter, a short-channel effect tends to occur, and the source and drain regions are short-circuited (punchthrough phenomenon), which causes serious trouble. In addition to this buried channel structure, when P+ source and drain regions are formed by an ordinary boron (B), the diffusion coefficient of boron is large, and penetration in the lateral direction from the gate end and the junction depth of the source and drain both become large, which is another cause of punchthrough.
Accordingly, in order to cope with such problems, as disclosed in the Japanese Patent Publication No. 61-160976, a p channel MOS transistor is constructed by using an effective punchthrough stopper (EPS) as shown in FIG. 2. That is, by disposing a sidewall, the overlap length of the gate electrode end and p+ source and drain region is minimized, and an EPS region (n+ region) is provided in the vicinity thereof.
As an example of such a process, a manufacturing method of a p-channel EPS structure MOS transistor is explained while referring to 2. First, after the element isolation process of the n-type semiconductor substrate or n-well 8, a p-type buried channel 9 is formed. Afterwards, by forming a gate insulator film 2, a polysilicon film is deposited, and is etched to form a gate electrode 3 [FIG. 2 (a)]. Next, in order to form EPS regions (n+ layers) 10s, 10d, a low concentration of ions A (phosphorus) are implanted using the gate electrode 3 as mask [FIG. 2 (b)]. Later, the CVD-SiO.sub.2 film is formed [FIG. 2 (c)], and anisotropically etched. The CVD-SiO.sub.2 film 6 formed on the flat surface is removed, and a sidewall 7 of CVD-SiO.sub.2 film 6 is formed on the periphery of the gate electrode 3 [FIG. 2 (d)]. Then, in order to form the desired source and drain regions (p+ layers) 11s, 11d, a high concentration of ions B(BF.sub.2 or B) are implanted using the gate electrode 3 and sidewall 7 as a mask [FIG. 2 (e)]. At this time, the sidewall 7 impedes the ion implantation onto the semiconductor surface, and source and drain regions (p+ layers) 11s, 11d, and EPS regions (n+ layers) 10s, 10d are formed. Finally, by heat treatment, a p-channel EPS structure MOS transistor is formed as shown in FIG. 2 (e).
Thus, in the conventional EPS structure MOS transistor, by building up a structure possessing EPS regions, the EPS regions (n+ layers) 10s, 10d operate to inhibit the elongation of potential from the drain region 11d by the drain voltage, which is effective to suppress the short channel effect and punchthrough phenomenon.
However, the ion implantation A is close to the vertical direction (usually inclining 7.degree. to prevent channeling), and penetration of EPS regions 10s, 10d from the end of gate electrode 3 is small. The EPS regions 10s, 10d are likely to diminish by the diffusion in the lateral direction of the source and dram regions 11s, 11d due to the subsequent high concentration ion implantation B and heat treatment. In order to avoid this, it is indispensable to form a relatively thick sidewall 7 of about 0.25 .mu.m. Accordingly, the source and drain regions 11s, 11d are nearly matched with the gate electrode 3 end by self-aligning of the high concentration ion implantation B by the gate electrode 3 with using the sidewall 7, the EPS structure MOS transistor has the following demerits as compared with the conventional single source/drain structure MOS transistor.
(1) For control of the diffusion in the lateral direction of the source and drain regions 11s, 11d after high treatment or the width of sidewall 7, certain fluctuations occur in the process, and the ends of the source and drain regions 11s, 11d may come outside the gate electrode 3, not matching at all. In such cases, a channel region is also formed just outside the gate electrode 3, and the gate controllability in the channel region in this area is lowered significantly to cause pinchoff, resulting in a resistance increase. In consequence, the driving current is lowered, and a high electric field is formed in this portion, and therefore the deterioration due to hot carriers becomes a more serious problem than in the conventional single source/drain structure,
(2) Comparing the width of gate electrode 3, the effective channel length of the EPS structure MOS transistor in FIG. 4 is longer by the portion of the double width of the sidewall 7, and accordingly the driving current is lowered.
Furthermore, the LDD structure MOS transistor in FIG. 1 and the EPS structure MOS transistor in FIG. 4 possess the following problems as compared with the conventional single source/drain structure MOS transistor. That is, in the step of forming the source and drain regions, in order to avoid the channeling effect of impurities when implanting ions, ions are implanted at a certain inclination angle (generally about 7.degree.) relative to the vertical direction of the semiconductor surface. Accordingly, when ions were implanted from the drain (or source) region side to the gate electrode, the portion adjacent to the gate electrode in the source (or drain) region on the opposite side came under the shadow, impurities were not implanted, the transistor structure became asymmetric, and an asymmetry occurred in the transistor characteristic depending on the direction of the source or drain. Such a problem of asymmetricity may be mostly ignored in a high concentration layer such as the source and drain desired in the structure, but it is known to be serious 4-n the case of LDD regions (n- layers) 4s, 4d in FIG. 1, or EPS regions (n+ layers) 10s , 10d in FIG. 4. To solve the problem of asymmetry, U.S. Pat. No. 4,771,012, one of the authors of which is an inventor of this invention, has proposed a method of fabricating a MOS transistor by repeating ion implation steps by rotating the semiconductor substrate in planarity.